An asynchronous flash memory with a page mode read feature reads out a page of four words at every memory access. When configured in synchronous mode, the memory device must perform sequential reads starting from an initial address. Four words at once are always read. In the existing state of the art, several column decoder architectures have been proposed to implement the above mentioned reading parallelism.
FIG. 1 illustrates a conventional column decoder for a single bit of a word. Here, four words are simultaneously read by means of four sense amplifiers (SA) 102. Each SA 102 is connected through three levels of decoding stages 103-105 to 128 bit lines (BL). The selector multiplexer 101 is used to actively choose one word among the four reads. The signals that control the three levels of decoding stages 103-105 are common for all the bits of the four words, and each group of four words (a logical page) has its own selector multiplexer 101. The resulting total number of selector multiplexers is equal to the bit length of a read word, that in turn is equal to the number of outputs.
For example, suppose that the subdivision of the column decoding control bits and selector multiplexer control bits is as follows:                2 address bits used to choose one word among the four reads: ADD<1:0>. This choice follows directly from the memory device's specifications, which demands a scrolling of the read page in asynchronous mode by commuting the two less significant bits of the address.        7 address bits used to address the 128 cells (bits) in the matrix array: ADD<8:2>        
As illustrated in FIG. 2, assume that these 7 bits are used to implement the three levels of column decoding states 103-105 in the following way:                ADD<8:6> decode 8 independent signals (YD)        ADD<5:4> decode 4 independent signals (YN)        ADD<3:2> decode 4 independent signals (YM)        
The architecture of the column decoder is hence the following:                The local BL selectors YD sel<7:0> form the first level 105 of the column decoder. These selectors connect the drains of the array cells (local BLs) to the global BLs running all over the device. Each sector has its own set of YD sel<7:0> and its own local BLs. Each of the 16 global BLs is connected via YD sel<7:0> gated by the eight YD<7:0> signals) to eight cells in the array, for a total of 128 bits per output.        The 16 global BLs enter the second level of column decoder stage 104, which includes four groups of selectors, each group being made of four YN sel<3:0> selectors. They are gated by the four YN<3:0> signals. The four global BLs of each group are connected via YN sel<3:0> to a main BL, for a total of four main BLs, each connected to a group of four global BL.        The four main BLs enter the third level of column decoder stage 103, which includes a group of four selectors YM sel<3:0>, gated by YM<3:0> signals. These selectors connect in turn one of the four main BLs to the sense BL that feeds the sense circuitry.        
However, this architecture has a significant limitation in performing reads of groups of consecutive words starting from a word whose initial address is not a multiple of four, or, is “misaligned” to a 4-word boundary. In this case, the read implies what is called a logical page boundary crossing. In this specification, a 4-word boundary will be referred to as a “logical page boundary”, and 4 words whose addresses only differ for ADD<4:0> will be referred to as words belonging to the same logical page. Only the words within the logical page addressed by the first word to be read are valid. The memory device then enters a “wait state”, during which invalid data are supplied to the output, negatively impacting the performance of the column decoder. The possibility of having wait states occurs in burst mode reading, when consecutive words must be read out from the matrix array starting from an arbitrary address. Some types of burst reads actually imply a logical page boundary crossing.
Accordingly, there exists a need for an improved method and device for column decoding for flash memory devices. The improved method and device should minimize the need for the memory device to enter the wait state when a misalignment of the initial address of a read occurs. The present invention addresses such a need.